1. Field of Use
The present invention relates to electronic integrated circuits (ICs) and, more particularly, to circuits which employ a standard boundary scan test access port.
2. Prior Art
A standard boundary scan test architecture was approved by the American National Standards Institute (ANSI) and the Institute of Electrical and Electronics Engineers (IEEE) in 1990. Major revisions were approved in 1993 and 1994 as part of an ongoing evolutionary process. This architecture provides a means by which ICs may be designed in a standard fashion such that they or their external connections, or both, may be tested using a four or five wire interface.
The roots of boundary scan testing are found in the scan test methodology developed in the 1960s. An example of one implementation of this technology is described in U.S. Pat. No. 3,582,902, granted Jun. 1, 1971. The basic scan concept is to join all storage elements (e.g., flip-flops) of a logic design in one or more serial strings. The serial, or shift register, interconnection is in addition to the normal functional interconnection, and is intended to be primarily used during testing. Although this hardly makes the testing of complex systems easy to accomplish, scanning reduces the overwhelming chore of simulating sequential systems to the more manageable chore of simulating combinatorial systems.
It is important to note that the addition of scan circuitry does not benefit the functional role of the logic system to which it is added. Test circuitry is deemed undesirable overhead which would not be included if there were other practical ways of eliminating faults. Therefore, test simplification is a powerful economic incentive.
The complexities which arise from the use of the basic scan concept were the motivation behind the development of the boundary scan test architecture. Developing a test for a design using the original scan concept required simulating large sections of a system, or an entire system. During diagnosis, failing tests often could not be readily correlated with actual faults. The reason was that any one error indication sensed at the test system could be the result of one or more of a large number of faulty devices or interconnects, even when it was assumed that the integrity of the scan string was intact (i.e., provided a fault free path).
In the boundary scan test architecture, a serial string is placed at the periphery of the IC, independent of storage element locations. A four or five wire interface between the various ICs of a system so designed to include the boundary scan test architecture in conjunction with a test system allows separate and isolated testing of the ICs and the connections between them. The end result provides a much simplified correlation between failing tests and physical faults.
Until recently, scan testing has been regarded as purely digital. While methods have been proposed to test analog devices in conjunction with digital scan testing, they often share the approach of converting analog signal levels to digital signal levels and vice-versa as part of the interface between the test system and the analog devices to be tested. Where such conversion must be avoided, separate interconnections from the digital serial string are made between the test system and the analog devices to be tested. In this case, the digital serial string serves merely as part of a routing control mechanism for the analog signals.
Although the ability to accomplish analog testing with the same overhead test circuitry as used for digital testing is most desirable, until now implementing such an arrangement has been generally viewed as impractical. For example, separate IEEE working groups are developing different digital and analog test bus standards. It is generally the view in the testing field that in-circuit testers will not be replaced regardless of strides made in boundary scan testing because analog device testing is beyond the reach of the standard boundary scan architecture. Position papers presented at the 1992 IEEE International Test Conference in conjunction with a panel on mixed signal testing (proceedings pp. 555-557) indicate separate package pins might be used in an analog test architecture for analog test purposes, in addition to the pins used in the boundary scan architecture. Presently, a standard founded in this architecture is being considered by the IEEE P1149.4 Working Group.
Significant benefit would be derived if were it possible to test analog devices utilizing the four or five package pin overhead test circuitry already largely found acceptable in the industry used to accomplish digital testing via boundary scan. This could often eliminate the need for in-circuit test stations in manufacturing. Also, this could often avoid the use of test points to accommodate such analog testing in printed circuit board designs involving optimum miniaturization. Furthermore, this could allow for analog testing at the internal IC device level.
Previously, U.S. Pat. No. 5,404,358 supported such analog testing but had the disadvantage of making connection to the analog points to be measured through other devices comprising the boundary scan chain in what might be termed an indirect connection method. The connections were made through a series of analog switches--one or more for each IC device between the end of the boundary scan chain and the point to which connection was desired. The resistance of the series of analog switches limits practical application of this technique. The method using extra pins has no such disadvantage.
Recently, another architecture has been proposed wherein the digital test mode select (TMS) input pin of the TAP serves as a mixed-signal pin and is used for stimulus during analog measurements and for logic input during control of the state transitions of the TAP's finite-state machine (TAP controller). The architecture is proposed for use in architectures having two analog buses AB1 and AB2 with identical switching networks for each I/O pin. When so used, this architecture requires one less test pin per IC by providing a common pin TMS/AB1 used for causing TAP controller state transitions and analog signals. To carry out such analog measurements with the architecture, it is required that the TAP test clock (TCK) input pin be stopped or frozen at zero.
While the above architecture reduces the number of input pins, it still requires an additional pin per each IC device for carrying out analog testing. Also, it requires that the test clock input pin be held in a single state. That is, proper operation of the architecture is dependent upon that pin. It cannot be used for other purposes, such as becoming another analog signal pin.
For a further more detailed discussion of the above architecture, reference may be made to paper 25.2 entitled, "Integration of EEEE Std. 1149.1 and Mixed-Signal Test Architectures" by David J. Cheek and R. Dandapani, published in the International Test Conference Proceedings, Copyrighted.COPYRGT. 1995.
Accordingly, it is a primary object of the present invention to provide a method and apparatus for analog and digital signal processing by an interface generally compatible with a standard boundary scan architecture.
It is a further object of the present invention to provide a method and means of testing analog components and devices utilizing such interface in conjunction with current digital scanning techniques.
It is a still further object of the present invention to provide the method and means for an analog interface which has no significant detriment to the digital scanning techniques already in place.
It is an even still further object of the present invention to allow direct connection between an IC device within a series of IC devices of a boundary scan chain and analog measurement equipment external to the IC devices.